# Copyright (c) 2009 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
#          Brad Beckmann

from m5.params import *
from m5.SimObject import SimObject
from MemoryControl import MemoryControl

class RubyMemoryControl(MemoryControl):
    type = 'RubyMemoryControl'
    cxx_class = 'RubyMemoryControl'
    cxx_header = "mem/ruby/system/RubyMemoryControl.hh"
    version = Param.Int("");

    # Override the default clock
    # Praveen: /RubyMemoryControl.cc contains multiplier for this freq in wakeup()
    clock = '400MHz'
    banks_per_rank = Param.Int(4, "");
    ranks_per_dimm = Param.Int(2, "");
    dimms_per_channel = Param.Int(1, "");
    bank_bit_0 = Param.Int(12, "");
    rank_bit_0 = Param.Int(14, "");
    dimm_bit_0 = Param.Int(15, "");
    
    #bank_bit_0 = Param.Int(12, "");
    #rank_bit_0 = Param.Int(14, "");
    #dimm_bit_0 = Param.Int(15, "");
    
    bank_queue_size = Param.Int(12, "");
    bank_busy_time = Param.Int(18, "");
    rank_rank_delay = Param.Int(1, "");
    read_write_delay = Param.Int(2, "");
    basic_bus_busy_time = Param.Int(2, "");
    mem_ctl_latency = Param.Cycles(16, "");
    refresh_period = Param.Cycles(1560, "");
    tFaw = Param.Int(0, "");
    mem_random_arbitrate = Param.Int(0, "");
    mem_fixed_delay = Param.Cycles(0, "");
    mem_open_page_policy = Param.Int(1, "");
    mem_frfcfs_policy = Param.Int(1, "");
    #use frfcfs with open page policy only
    m_mem_rowbuffer_hit_latency = Param.Cycles(14, "");
    m_mem_rowbuffer_conflict_latency = Param.Cycles(32, "");

    mem_two_queues = Param.Int(1, "");
    mem_prioritize_cpu = Param.Int(1, "");
    mem_blp_aware_ip_mem = Param.Int(1, "");

##// DDR3-1600 parameters (10-10-10)
##// data burst = 4
##//## activate = 10
##MEM_BUS_CYCLE_MULTIPLIER: 4
##BASIC_BUS_BUSY_TIME: 4
##// MEMORY_PRECHARGE_TIME: 10
##ROWBUFFER_HIT_BUSY_TIME: 14 // bank access + data burst
##ROWBUFFER_HIT_LATENCY: 14  // bank access + data burst
##ROWBUFFER_CONFLICT_BUSY_TIME: 34 // precharge + activate + bank access + data burst
##ROWBUFFER_CONFLICT_LATENCY: 34 // precharge + activate + bank access + data burst
##BANK_BUSY_TIME: 26  // activate + bank access + data burst + auto-precharge
##MEM_CTL_LATENCY: 24 // activate + bank access + data burst

## for 400Mhz, 1 hz(memory cycle) = 2.5ns
##assuming, (15ns , 15ns, 18ns) for TRcd, TCL, TRp => translates to (6,6,7) cycles.
##// data burst = 4
##// activate = 6
##// MEMORY_PRECHARGE_TIME: 7
##ROWBUFFER_HIT_BUSY_TIME: 10 // bank access + data burst 
##ROWBUFFER_HIT_LATENCY: 10  // bank access + data burst
##ROWBUFFER_CONFLICT_BUSY_TIME: 23 // precharge + activate + bank access + data burst
##ROWBUFFER_CONFLICT_LATENCY: 23 // precharge + activate + bank access + data burst
##BANK_BUSY_TIME: 18  // activate + bank access + data burst + auto-precharge
##MEM_CTL_LATENCY: 16 // activate + bank access + data burst
